This application claims priority to Japanese Patent Application Number 2000-297663 filed Sep. 28, 2000, the content of which is incorporated herein by reference in its entirety.
1. Field of the Invention
The present invention relates to a reset device (or apparatus) for detecting, for example, a rise of a supply voltage so as to start outputting a reset signal and then releasing the reset signal, and a semiconductor IC apparatus (or device) and a semiconductor memory apparatus (or device) including the reset device.
2. Description of the Related Art
Conventional techniques for resetting for initialization of a system include, for example, (i) so-called hardware reset by which the system is allowed to be initialized from a terminal dedicated to resetting, asynchronously with the operation of the system, (ii) power-on reset by which a reset signal for initializing a system is automatically generated when the power is turned on, and (iii) software reset by which the system is initialized by generating a reset signal by interpreting a command which is input from an external device. The power-on reset used in a conventional reset device will be described.
The reset device includes a supply voltage detection circuit for detecting a supply voltage by some method in order to determine whether the power is turned on or not, and a reset signal output circuit for starting to output a reset signal and then releasing the reset signal based on the detection of the supply voltage.
FIG. 4 shows a simple example of a circuit configuration of such a conventional reset device. Referring to FIG. 4, a reset device 100 includes a supply voltage detection circuit 101 including a capacitor C (dielectric capacitor) and a resistor R connected in series, and a reset signal output circuit 104 including a first-stage inverter 102 and a second-stage inverter 103 connected in series. The inverters 102 and 103 each include a p-channel MOS transistor (hereinafter, referred to as the xe2x80x9cp-channel Tr) and an n-channel MOS transistor (hereinafter, referred to as the xe2x80x9cn-channel Tr).
Due to the above-described structure, when the supply voltage rises, the capacitor C of the supply voltage detection circuit 101 is charged through the resistor R at a prescribed time constant RC. The voltage which is generated at the resistor R by the charging current is given to the first-stage inverter 102, including the p-channel Tr and the n-channel Tr, through a node N105. At this point, the capacitor C is not charged rapidly. The node N105 is in a logical xe2x80x9clowxe2x80x9d state, and the reset signal which is output from the reset signal output circuit 104 is also in an active logical xe2x80x9clowxe2x80x9d state.
Next, when the potential of the node N105 increases as the capacitor C is more and more charged and exceeds a gate threshold voltage which is mainly determined by the threshold voltages and the driving capabilities of the p-channel Tr and the n-channel Tr of the first-stage inverter 102, the output of the first-stage inverter 102 inverts to a logical xe2x80x9clowxe2x80x9d state. The logical xe2x80x9clowxe2x80x9d output is sent to the second-stage inverter 103, and inverted into a logical xe2x80x9chighxe2x80x9d state. Thus, the reset signal which is output from the reset signal output circuit 104 is released. A value of the time constant RC of the capacitor C and the resistor R (Cxc3x97R) is appropriately selected so that the supply voltage is at a sufficiently high level for a sufficiently long reset time which is required for the system. The reset time is a time period from when the output of the reset signal is started until the reset signal is released.
However, when the rise of the supply voltage when the power is turned on is sufficiently slow such that the capacitor C is fully charged only at the end of a duration corresponding to the time constant RC, there is an undesirable possibility that the potential of the node N105 does not reach the gate threshold voltage of the inverter 102, and as a result, the reset signal from the reset signal output circuit 104 may not be released.
In order to avoid such an inconvenience, a reset signal device 200 shown in FIG. 5 including a supply voltage detection circuit dedicated to the case when the supply voltage slowly rises and another supply voltage detection circuit dedicated to the case when the supply voltage rapidly rises is used. Referring to FIG. 5, the reset device 200 includes a supply voltage detection circuit 201 operating when the supply voltage slowly rises, a supply voltage detection circuit 202 operating when the supply voltage rapidly rises, and a reset signal output circuit 203 for starting to output a reset signal and releasing the reset signal in accordance with signals input from the supply voltage detection circuit 201 and 202.
The supply voltage detection circuit 201 has the following structure. Resistors R1 and R2 are connected in series between a power supply and the ground. A node N1, which is a dividing point (i.e., a connection point) between the resistors R1 and R2, is connected to one of two ends of a capacitor C1 (dielectric capacitor) and to a gate of an n-channel Tr M1. The other end of the capacitor C1 is connected to the power supply. A source of the n-channel Tr M1 is grounded, and a drain of the n-channel Tr M1 is connected to the power supply via a pull-up resistor R3. A node N2, which is a connection point between the n-channel Tr M1 and the pull-up resistor R3, is connected to an input end of an inverter 210 including a p-channel Tr M2 and an n-channel Tr M3.
The supply voltage detection circuit 202 has the following structure. A p-channel Tr M4, a resistor R4, and an n-channel Tr M5 and another n-channel Tr M6 each having a gate connected to a power supply are connected in series in this order. A node N3, which is a connection point between the n-channel Tr M5 and the resistor R4, is connected to a capacitor C2 (dielectric capacitor) and to an input end of an inverter 220 including a p-channel Tr M7 and an n-channel Tr MB. To a gate of the p-channel Tr M4, a reset signal is input as a result of being fedback.
The reset signal output circuit 203 includes a negative OR circuit, which includes a NAND circuit NAND1 for receiving an output from each of the supply voltage detection circuits 201 and 202, and an inverter 230 for receiving an output from the NAND circuit NAND1 and starting to output a reset signal or releasing the reset signal. The inverter 230 includes a p-channel Tr M9 and an n-channel Tr M10.
The n-channel Trs M8 and M10 each have a low threshold voltage, and thus are specifically indicated as in FIG. 5.
Hereinafter, an operation of the reset device 200 when the supply voltage slowly rises will be described.
Immediately after the power is turned on, the potential of the node N2 is in a logical xe2x80x9chighxe2x80x9d state as a result of being pulled up via the resistor R3. Therefore, the output from the inverter 210 (i.e., the output from the supply voltage detection circuit 201) is in a logical xe2x80x9clowxe2x80x9d state. Thus, the output from the NAND circuit NAND1 is in a logical xe2x80x9chighxe2x80x9d state regardless of whether the input from the supply voltage detection circuit 202 is in a logical xe2x80x9chighxe2x80x9d state or a logical xe2x80x9clowxe2x80x9d state. Therefore, the reset signal, which is output from the inverter 230 (i.e., the output from the reset signal output circuit 203), is in an active logical xe2x80x9clowxe2x80x9d state (i.e., the state of outputting a reset signal).
In the case where the supply voltage slowly rises, even when a sufficient amount of current does not flow into the capacitor C1, a potential which is lower than the supply voltage divided into the resistors R1 and R2 connected in series is input to the gate of the n-channel Tr M1 via the node N1. When the potential of the node N1 exceeds the threshold voltage of the n-channel Tr M1, the n-channel Tr M1 is activated. Therefore, the node N2 is transferred from the logical xe2x80x9chighxe2x80x9d state obtained immediately after the power is turned on into a logical xe2x80x9clowxe2x80x9d state. Thus, the output from the inverter 210 is logically inverted into a logical xe2x80x9chighxe2x80x9d state. Then, a logical xe2x80x9chighxe2x80x9d output is sent from the supply voltage detection circuit 201 to the NAND circuit NAND1.
In the supply voltage detection circuit 202, since the supply voltage rises sufficiently slowly to charge the capacitor C2, the node N3 is placed into a logical xe2x80x9clowxe2x80x9d state via the n-channel Trs M5 and M6 which are activated as a result of the gates being connected to the power supply. Since the node N3 is in the logical xe2x80x9clowxe2x80x9d state, the output from the supply voltage detection circuit 202 is in a logical xe2x80x9chighxe2x80x9d state as a result of being inverted by the inverter 220. Therefore, a logical xe2x80x9clowxe2x80x9d output is sent from the NAND circuit NAND1 to the inverter 230. As a consequence, a reset signal which is output from the reset signal output circuit 203 is transferred from the active logical xe2x80x9clowxe2x80x9d state obtained immediately after the power is turned on into a logical xe2x80x9chighxe2x80x9d state and thus is released.
The reset signal from the reset signal output circuit 203 is in the logical xe2x80x9chighxe2x80x9d state as described above. The output from the supply voltage detection circuit 201 is more effective than the output from the supply voltage detection circuit 202. The reset signal from the reset signal output circuit 203 is as effective as the output from the supply voltage detection circuit 201 (in a logical high state) which is output as a reset signal without the logical state thereof being changed and then released.
Next, an operation of the reset device 200 when the supply voltage rapidly rises will be described.
In the supply voltage detection circuit 201, since the supply voltage rapidly rises, the potential of the node N1 is raised to the supply voltage via the capacitor C1. As a result, the n-channel Tr M1 is activated and thus the node N2 is placed into a logical xe2x80x9clowxe2x80x9d state substantially simultaneously with the rise of the supply voltage. Therefore, the output from the inverter 210 is in a logical xe2x80x9chighxe2x80x9d state. Thus, an active xe2x80x9clowxe2x80x9d output is not sent from the supply voltage detection circuit 201.
In the supply voltage detection circuit 202, the potential of the node N3 is raised to the supply voltage via the capacitor C2 so as to activate the n-channel Tr M8. Even though the n-channel Trs M5 and M6 are connected in series to the ground, the potential of the node N3 is easily raised due to high resistances of the n-channel Trs M5 and M6. The activation of the n-channel Tr M8 provides a rapid response since the n-channel Tr M8 has a low threshold voltage. Substantially simultaneously with the rise of the supply voltage, the inverter 220 is placed into a logical xe2x80x9clowxe2x80x9d state and input to the NAND circuit NAND1. Therefore, the output from the NAND circuit NAND1 is in a logical xe2x80x9chighxe2x80x9d state regardless of whether the input to the NAND circuit NAND1 is in a logical xe2x80x9clowxe2x80x9d state or in a logical xe2x80x9chighxe2x80x9d state. As a consequence, a reset signal is output in an active logical xe2x80x9clowxe2x80x9d state. In the case where the supply voltage rapidly rises, the output from the supply voltage detection circuit 202 is more effective than the output from the supply voltage detection circuit 201.
Thereafter, the capacitor C2 is discharged via the n-channel Trs M5 and M6 which are activated by the rise of the supply voltage, and thus the node N3 is transferred into a logical xe2x80x9clowxe2x80x9d state. Thus, the output from the supply voltage detection circuit 202 is placed into a logical xe2x80x9chighxe2x80x9d state. As a consequence, a reset signal which is output from the reset signal output circuit 203 (negative OR circuit) is transferred from the active xe2x80x9clowxe2x80x9d state into a logical xe2x80x9chighxe2x80x9d state and thus is released.
While the reset signal is in the active logical xe2x80x9clowxe2x80x9d state, the logical xe2x80x9clowxe2x80x9d state is fedback to the gate of the p-channel Tr M4 so as to activate the p-channel Tr M4. A current flows to the n-channel Trs M5 and M6 via the resistor R4 and acts so as to inhibit the discharge of the charges accumulated in the capacitor C2. In this manner, a sufficient time period can be obtained until the reset signal is released.
When the discharge of the capacitor C2 is completed, the node N3 is placed into a logical xe2x80x9clowxe2x80x9d state, which places the output from the supply voltage detection circuit 202 into a logical xe2x80x9chighxe2x80x9d state. Thus, the reset signal is placed into a logical xe2x80x9chighxe2x80x9d state, which de-activates the p-channel Tr M4. Therefore, the serial path from the power supply to the ground via the p-channel Tr M4, the resistor R4, the n-channel Tr M5 and the n-channel Tr M6 is broken, and the DC current flowing thereafter is cut off.
The reset device 200 shown in FIG. 5 has the following problems.
(1) Since a serial circuit of the resistors R1 and R2 is connected between the power supply and the ground in the supply voltage detection circuit 201, a serial path is made even after the supply voltage rises. As a result, even after the supply voltage rises, the current still flows in the serial circuit of the resistors R1 and R2, which unnecessarily increases the power consumption.
(2) It is necessary to switch the supply voltage detection circuit 201 or 202 depending on whether the supply voltage rises slowly or rapidly. The switching operation relies on the capacitances of the capacitors C1 and C2, the resistances of the resistors R1 through R4, and characteristics of the transistors M1 through M10 as parameters of the supply voltage detection circuits 201 and 202. In consideration of the dispersion of the capacitances, the resistances and the characteristics, it is difficult to control the parameters so as to stably perform the switching operation.
(3) Today, it is strongly desired to reduce the power consumption, as an increasing number of devices designed so as to be driven by batteries are provided. It has become essential that the system should operate at a low supply voltage to significantly contribute to the energy savings. Under the circumstances, a power-on reset circuit which stably performs a reset operation even at a low voltage is demanded.
A reset device according to the present invention detects a rise of a supply voltage to start outputting a reset signal and then to release the reset signal. The reset device comprising a voltage detection circuit for detecting the supply voltage. The voltage detection circuit includes a ferroelectric capacitance element for detecting a rise of the supply voltage.
In one embodiment of the invention, the reset device further includes a reset signal output section for generating a reset signal using a polarization characteristic of the ferroelectric capacitance element, and a reset signal release section for releasing the reset signal.
In one embodiment of the invention, the reset device further includes an initial polarization state setting section for determining a polarization state of the ferroelectric capacitance element.
In one embodiment of the invention, the reset device further includes a polarization state initialization section for returning the polarization state of the ferroelectric capacitance element to an initial polarization state after the reset signal is released.
In one embodiment of the invention, the polarization state initialization section includes a pulse generation circuit having an input end connected to an input end of a first inverter of the voltage detection circuit, the polarization state initialization section generating a polarization state initialization pulse from an output end thereof to a second end of the ferroelectric capacitance element.
In one embodiment of the invention, the reset signal release section includes a second inverter, a second pass transistor, a delay circuit, and a reset signal release transistor. A connection point between a pull-up resistor and a reset signal driving transistor is connected to an input end of the second inverter. The input end of the second inverter is connected to a control terminal of the second pass transistor. An output end of the second inverter is connected to one of two driving terminals of the second pass transistor. The other driving terminal of the second pass transistor is connected to an input end of a first inverter via the delay circuit. The input end of the first inverter is connected to a control terminal of the reset signal release transistor. One of two driving terminals of the reset signal release transistor is connected to a control terminal of the reset signal driving transistor. The other driving terminal of the reset signal release transistor is grounded.
In one embodiment of the invention, the reset signal output section includes a reset signal driving transistor and a pull-up resistor. A second end of the ferroelectric capacitance element is connected to a control terminal of the reset signal driving transistor via a first pass transistor, which has a control terminal connected to an output end of a first inverter. One of two driving terminals of the reset signal driving transistor is connected to a first end of the pull-up resistor, which has a second end connected to a power supply. The other driving terminal of the reset signal driving transistor is grounded.
In one embodiment of the invention, the reset signal release section includes a second inverter, a second pass transistor, a delay circuit, and a reset signal release transistor. A connection point between the pull-up resistor and the reset signal driving transistor is connected to an input end of the second inverter. The input end of the second inverter is connected to a control terminal of the second pass transistor. An output end of the second inverter is connected to one of two driving terminals of the second pass transistor. The other driving terminal of the second pass transistor is connected to an input end of the first inverter via the delay circuit. The input end of the first inverter is connected to a control terminal of the reset signal release transistor. One of two driving terminals of the reset signal release transistor is connected to the control terminal of the reset signal driving transistor. The other driving terminal of the reset signal release transistor is grounded.
In one embodiment of the invention, the reset device further includes a polarization state initialization section for returning a polarization state of the ferroelectric capacitance element to an initial polarization state after the reset signal is released.
In one embodiment of the invention, the polarization state initialization section includes a pulse generation circuit having an input end connected to an input end of a first inverter of the voltage detection circuit, the polarization state initialization section generating a polarization state initialization pulse from an output end thereof to a second end of the ferroelectric capacitance element.
In one embodiment of the invention, the polarization state initialization section has a structure in which a pull-down transistor is connected to a first end of the ferroelectric capacitance element, and a pull-up transistor is connected to a second end of the ferroelectric capacitance element.
In one embodiment of the invention, the reset device further includes an initial polarization state setting section for determining a polarization state of the ferroelectric capacitance element.
In one embodiment of the invention, the reset device further includes a polarization state initialization section for returning the polarization state of the ferroelectric capacitance element to an initial polarization state after the reset signal is released.
In one embodiment of the invention, the polarization state initialization section includes a pulse generation circuit having an input end connected to an input end of a first inverter of the voltage detection circuit, the polarization state initialization section generating a polarization state initialization pulse from an output end thereof to a second end of the ferroelectric capacitance element.
In one embodiment of the invention, the polarization state initialization section has a structure in which a pull-down transistor is connected to a first end of the ferroelectric capacitance element, and a pull-up transistor is connected to a second end of the ferroelectric capacitance element.
In one embodiment of the invention, the voltage detection circuit detects the rise of the supply voltage by a polarization inversion so that the reset signal is generated by a transfer of a potential of the ferroelectric capacitance element caused by the polarization inversion.
In one embodiment of the invention, the voltage detection circuit includes a first inverter. An input end of the first inverter is grounded via a dielectric capacitance element and a pull-down resistor. An output end of the first inverter is connected to a first end of the ferroelectric capacitance element.
In one embodiment of the invention, the voltage detection circuit includes a first inverter. An input end of the first inverter is grounded via a dielectric capacitance element and a pull-down resistor. An output end of the first inverter is connected to a first end of the ferroelectric capacitance element.
According to another aspect of the invention, a semiconductor IC apparatus includes the above-described reset device which is formed using a semiconductor material.
According to still another aspect of the invention, a semiconductor memory apparatus includes the abovedescribed semiconductor IC apparatus.
According to the present invention, the ferroelectric capacitance element provided in the voltage detection circuit keeps a residual polarization due to the hysteresis characteristic thereof and thus does not charge or discharge relying on time unlike a dielectric capacitor. Therefore, consumption of a current during the operation of the circuit and a serial path required in the conventional art can be eliminated. As a result, constant current consumption is eliminated, resulting in reduced power consumption. By selecting an appropriate ferroelectric material used for the ferroelectric capacitance element and an appropriate thickness of the ferroelectric capacitance element, the polarization inversion voltage can be minimized. Thus, a stable operation is guaranteed even at a low voltage. The polarization caused to the ferroelectric material is spontaneous polarization induced by the electric field applied thereto and thus does not accompany injection or release of charges to or from an external device unlike the dielectric capacitor. Therefore, the polarization inversion is performed rapidly. The polarization inversion is controlled only by an electric field, i.e., a voltage supplied from an external device. Therefore, the polarization inversion does not rely on the rising time of the voltage, and a voltage detection circuit which is sufficiently easily controlled is realized. As a result, a reset circuit providing a stable operation is realized.
According to the present invention, a reset signal can start being output and then be released relatively easily using a polarization characteristic of the ferroelectric capacitance element.
According to the present invention, the initial polarization state of the ferroelectric capacitor can be easily and arbitrarily determined by the initial polarization state setting section.
According to the present invention, after the supply voltage rises to release the reset signal, the polarization state of the ferroelectric capacitance element can be easily and automatically returned to the initial polarization state by the polarization state initialization section.
According to the present invention, the polarization of the ferroelectric capacitance element is inverted upon a rise of the supply voltage. Using the charge generated at this point, a reset signal can be generated rapidly and easily.
According to the present invention, the voltage detection circuit can have a simple structure using the ferroelectric capacitance element.
According to the present invention, a reset signal output section having a structure which is suitable to a voltage detection circuit using the ferroelectric capacitance element and is simple can be realized.
According to the present invention, a reset signal release section for releasing the reset signal after starting the output of the reset signal can be realized with a simple structure.
According to the present invention, an initial polarization state setting section can be realized with a simple structure.
According to the present invention, a polarization state initialization section can be realized with a simple structure.
A reset device (or apparatus) according to the present invention can be easily adopted for a semiconductor IC apparatus.
A semiconductor IC apparatus (or device) adopting a reset device (or apparatus) according to the present invention can be easily adopted for a semiconductor memory apparatus (or device).
Thus, the invention described herein makes possible the advantages of providing a reset device which operates without relying on control by parameters for performing a stable switching operation, reduces power consumption, and guarantees a stable operation even at a low voltage; and a semiconductor IC apparatus and a semiconductor memory apparatus including such a reset device.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.